1 Introduction. - 1. 1 The Process of IC Design. - 1. 2 Layout Styles. - 1. 3 Timing-driven Layout. - 1. 4 Outline of the Book. - 2 Delay Estimation. - 2. 1 Introduction. - 2. 2 Micromodeling The RC Model. - 2. 3 Macromodeling. - 2. 4 Worst-case Delay Estimation. - 2. 5 Delay Calculation at the Circuit Level. - 2. 6 Posynomial Delay Modeling. - 2. 7 A Case Study: iCONTRAST's Timing Analyzer. - 2. 8 Summary. - 3 Transistor Sizing Algorithms: Existing Approaches. - 3. 1 Introduction. - 3. 2 The TILOS Algorithm. - 3. 3 The Method of Feasible Directions (MFD) Algorithm. - 3. 4 Lagrangian Multiplier Approaches. - 3. 5 Two-step Optimization. - 3. 6 Other Approaches. - 3. 7 Summary of Previous Approaches. - 4 A Convex Programming Approach to Transistor Sizing. - 4. 1 Introduction. - 4. 2 The Convex Programming Algorithm. - 4. 3 Experimental Results. - 4. 4 Summary. - 5 Global Routing Using Zero-one Integer Linear Programming. - 5. 1 Introduction. - 5. 2 Extracting Global Routing Information. - 5. 3 Global Routing Phases. - 5. 4 Global Routing on Medium-sized Arrays. - 5. 5 Application to Custom Logic Layout. - 5. 6 Handling Very Large Circuits. - 5. 7 Runtime Complexity. - 5. 8 Conclusion. - 6 Timing-driven CMOS Layout Synthesis. - 6. 1 Introduction. - 6. 2 A Methodology for Designing CMOS Standard Cells. - 6. 3 The Metal-Metal Matrix (M3) Layout Style for Two level Technologies. - 6. 4 iCGEN: A CMOS Layout Synthesis System for Three-level Metal Technology. Language: English